Yadala Sucharitha, P. Anantha Christu Raj, T. S. Karthik, Dhiraj Kapila, V.Mathiazhagan and Ranjan Walia
Portable encryption plays a key role in the emergence of computer applications in resource-controlled settings based on identification. In this document, we displayed higher resource-efficient VLSI Configurations for both 80-bit and 128-bit PRESENT cryptosystem Algorithms, called PRESET-80 and PRESET-128. These designs' FPGA implementations were carried out using a Xilinx XC6VXX70R-1-VF1646 FPGA chip based on LUT 6 technology. These designs feature a 33-clock-cycle delay, run at 306, 84 MHz, and give a maximal clock frequency of 595,`08 Mbps. The two different designs were tested with each other. The design of PRESENT-80 has also been found to have 21% lower FPGA trims and an increase of 26% in output. The PRESET-128 design also needs 21% less FPGA splitting, a latency decrease of 28%, and a total output increase of 70%.
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